1. Field of the Invention
The present invention relates generally to an ultra low power adder with sum synchronization, and more particularly pertains to an ultra low power adder with sum synchronization which provides a power reduction method in the binary carry propagate adders by using a carry skip technique.
The present invention provides a technique for eliminating glitches at the adder outputs by preventing signal transitions at the sum outputs until the corresponding carry signals have reached their final values, which is achieved by adding a synchronization circuitry to the sum calculation path.
2. Discussion of the Prior Art
FIG. 1 shows a conventional prior art single bit adder. A conventional prior art multi-bit carry propagate adder consists of a plurality of single-bit adders as illustrated in FIG. 1. Each single bit adder consists of a sum circuitry 10 and a carry circuitry 12, each of which receives two data inputs A—i and B—i and a carry signal C—i. Various techniques exist for speeding up the carry propagation process, such as carry skip adder, carry select adder, etc. In most types of adders, the arrival of the carry signal C—i to inputs of individual single bit adders is delayed compared to the arrival of the data inputs A—i and B—i.
FIG. 2(a) illustrates an exemplary prior art multi-bit addition process wherein a number of single bit adders are connected in series with a carry output C—i from the first single bit adder to the second single bit adder, a carry output C—i+1 from the second single bit adder to the third single bit adder, and a carry output C—i+2 from the third single bit adder, and etc.
FIG. 2(b) illustrates waveforms for the second single bit adder of FIG. 2(a), and illustrates in (1) and (2) input signals A—i, B—i, and in (3) the delayed arrival of and spurious switching of the carry signal C—i, and in (4) the spurious switching of the final values of the sum signal.
The waveforms of FIG. 2 (b)(3) show that the carry signal C—i may undergo a number of spurious transitions before settling to a final value. This causes glitches and spurious switching at the sum output of the adder, as shown in FIG. 2 (b)(4). These glitches in turn lead to extra power dissipation in the circuitry generating the sum outputs. Although FIG. 2 shows a simple carry-ripple adder, the same problem exists in most conventional adders used commercially in industry.
Moreover, glitches at the outputs of the adder propagate to the data bus going to the unit using the adder, for example, to the register file, address generation unit, etc. Since these busses typically have a significant capacitive load, glitches at the adder outputs lead to even higher power dissipation.
As opposed to very high performance implementations, CMOS adder designs which are optimized for low power applications tend to have less stringent requirements in terms of the time necessary to accomplish an add operation. Therefore these kinds of adders use the carry propagate type of adder, due to the small number of transistors in such designs.
The following two major drawbacks exist in the prior art with respect to using carry propagate adders:                1. The small device size of such low power designs makes the carry propagate path slow. The carry skip technique is a well known way to speed up the carry path by bypassing blocks of adder cells. Another well known method called carry select calculates two results (one for carry input being binary “0” represented by a +Vss level, the other for binary “1” represented by a +Vdd level), and once the real carry is available, uses it as the select signal to decide which one of the precalculated results is the final answer of the add operation. These techniques minimize the number of logic blocks used in the carry propagate path for improved speed.        2. The time lag in the arrival of the two input operands and the carry input for every bit position causes spurious switching activity in the sum calculation circuitry. The present invention addresses and solves this problem.        